Freescale Semiconductor /MKE15Z7 /TSI /DATA

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Interpret as DATA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TSICNT0 (0)SWTS 0 (0)DMAEN 0 (00000)TSICH

TSICH=00000, SWTS=0, DMAEN=0

Description

TSI DATA Register

Fields

TSICNT

TSI Conversion Counter Value

SWTS

Software Trigger Start

0 (0): No effect.

1 (1): Start a scan to determine which channel is specified by TSI_DATA[TSICH].

DMAEN

DMA Transfer Enabled

0 (0): Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.

1 (1): DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.

TSICH

TSICH

0 (00000): For self-cap mode: Channel 0.

1 (00001): For self-cap mode: Channel 1.

2 (00010): For self-cap mode: Channel 2.

3 (00011): For self-cap mode: Channel 3.

4 (00100): For self-cap mode: Channel 4.

5 (00101): For self-cap mode: Channel 5.

6 (00110): For self-cap mode: Channel 6.

7 (00111): For self-cap mode: Channel 7.

8 (01000): For self-cap mode: Channel 8.

9 (01001): For self-cap mode: Channel 9.

10 (01010): For self-cap mode: Channel 10.

11 (01011): For self-cap mode: Channel 11.

12 (01100): For self-cap mode: Channel 12.

13 (01101): For self-cap mode: Channel 13.

14 (01110): For self-cap mode: Channel 14.

15 (01111): For self-cap mode: Channel 15.

16 (10000): For self-cap mode: Channel 16.

17 (10001): For self-cap mode: Channel 17.

18 (10010): For self-cap mode: Channel 18.

19 (10011): For self-cap mode: Channel 19.

20 (10100): For self-cap mode: Channel 20.

21 (10101): For self-cap mode: Channel 21.

22 (10110): For self-cap mode: Channel 22.

23 (10111): For self-cap mode: Channel 23.

24 (11000): For self-cap mode: Channel 24.

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